Accelerating Multi-Core Simulators
Abstract :
Simulation is an important means of evaluating new microarchitectures. With the
invention of multi-core (CMP) platforms, simulators are becoming larger and
more complex. However, with the availability of CMPs (i.e. host/hardware
processor) with larger caches and higher operating frequency, the wall clock
time required for simulating an application has become comparatively shorter.
Reducing this simulation time further is a great challenge, especially in the
case of multi-threaded workload due to indeterminacy introduced due to
simultaneously executing various threads. In this paper, we propose a
technique for speeding multi-core simulation. The model of the processor core
and cache are replaced with functional models, to achieve speedup. A
pre-constructed timed Petri net helps to estimate the execution time of the
processor and the memory access latencies are estimated using hit/miss
information obtained from the functional model of the cache. This model can be
used to predict performance of data parallel applications or multiprogramming
environment on CMP platform with various cache hierarchies and shared bus
interconnect. The error in estimation of the execution time of an application
is within 6%. The speedup achieved ranges between an average of 2x-4x over the
cycle accurate simulator.
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