Sapphire: A Framework to Explore Power/Performance
Implications of
Filed Architecture on Chip Multicore Platform
Sapphire is a multi-processor/multicore simulator where the memory hierarchy,
interconnect (network on chip) and offchip DRAM are parametrized and can be
configured to model various configurations. Sapphire addresses shortcomings in SESC
by integrating it with Ruby from the GEMS framework. Sapphire also integrates
Intacte, an
interconnect power model. DRAMSim models off-chip DRAM in great details. This
has been integrated with Ruby. Power consumed by DRAM is modelled using
MICRON power model. Thus Sapphire allows users to explore power and performance
implications of all main system components like processor, interconnect,
cache hierarchy and offchip DRAM.
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