Sub-Tagged Caches: Study of Variable Cache-Block Size Emulation
Siddhartha V Tambat, Sriram Vajapeyam and S Muthulaxmi

IISc-CSA-TR-2001-4
(July 2001)

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The performance of a cache of a given size depends significantly on the cache
block size. Previous studies have shown that insufficient memory bandwidth,
rather than raw memory latencies, will be the major obstacle to improving
system performance. The cache block size has a large and varying impact on
memory traffic and hit rate across programs, suggesting the need for variable
block size caches. We propose sub-tagged caches, which extend sub-blocked
caches by breaking up the address tag into a common block tag shared by all
sub-blocks and a sub-tag unique to the specific sub-block. Sub-tagged caches
allow words from different memory blocks to co-reside in a cache block, without
changing the critical hit access path, and thus emulate variable address block
sizes. Typically only a few address tag bits differ between the blocks involved
in a cache conflict, thus motivating sub-tagged caches. Performance evaluation
with SPEC2000 benchmarks shows that the miss ratio and memory traffic ratio of
a column-associative sub-tagged cache is comparable to that of a four-way
set-associative sub-blocked cache, while its average memory access time is 18%
better on average.

Dynamic sub-block prefetching in conjunction with a sub-tagged cache emulates
variable address and fetch block sizes. A comparative study of different
variable block caches shows that while no single cache organization is best
across all benchmarks, variable block size caches outperform fixed block size
caches for seven of the twelve benchmarks. Among the different variable block
size caches, the column-associative sub-blocked and sub-tagged caches seem to
perform the best. Column-associative sub-tagged caches uniformly outperform
direct-mapped decoupled sectored caches, while direct-mapped sub-tagged caches
perform better than decoupled sectored caches for nine of the twelve
benchmarks.


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