Experiments with a new dictionary based code-compression tool on a VLIW processor
J. Prakash, C. Sandeep, Priti Shankar and Y.N. Srikant

IISc-CSA-TR-2004-5
(July 2004)

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Filed on July 12, 2004
Updated on September 2, 2004


Abstract
Reducing program size is a desirable goal in the design of an embedded system, since memory occupies a relatively large silicon area. Instruction compression schemes equipped with random decompression facilities are one answer to this problem. For VLIW architectures having flexible instruction formats, this is a particularly challenging problem beacuse instructions do not have an uniform structure and hence offer limited scope for discovering repeated patterns that can be exploited for compression. We propose a new dictionary based scheme here and evaluate its compression and decompression performance for the TMS62X architecture by carrying out detailed simulations.

keywords: code compression, embedded systems, VLIW processors.


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[Updated at 2009-10-22T06:42Z]