Adaptive Power Optimization of Onchip SNUCA Cache on Tiled Chip Multicore Architecture using Remap Policy
Aparna Mandke, Bharadwaj Amrutur, Y.N.Srikant
Advances in technology have increased the number of cores and size of caches
present on chip multicore platforms(CMPs). As a result, leakage power
consumption of on-chip caches has already become a major power consuming
component of the memory subsystem. Hence, we propose to reduce leakage power
consumption in static nonuniform access cache(SNUCA) on a tiled CMP by
dynamically varying the number of used cache slices and shutting off unused
cache slices. A cache slice in a tile includes all cache banks present in
that
tile. Switched-off cache slices are remapped considering the communication
costs to reduce cache usage with minimal impact on execution time. This
saves leakage power consumption in switched-off L2 cache slices. On an
average, the remap policy achieves 41% and 49% higher EDP savings than
static and dynamic NUCA(DNUCA) cache policies on a scalable tiled CMP,
respectively.
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