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DTEND:20210609T120000Z
UID:e34d4e268099b54fcb689c2b8c93e249-153
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DESCRIPTION:Design, Implementation, and Analysis of a TLB-based Covert Channel on GPUs
URL;VALUE=URI:https://www.csa.iisc.ac.in/newweb/event/153/design-implementation-and-analysis-of-a-tlb-based-covert-channel-on-gpus/
SUMMARY:GPUs are now commonly available in most modern computing platforms. They are increasingly being adopted in cloud platforms and data centers due to their immense computing capability. In response to this growth in usage, manufacturers are continuously trying to improve GPU hardware by adding new features. However, this increase in usage and the addition of utility-improving features can create new, unexpected attack channels. In this thesis, we show that two such features—unified virtual memory (UVM) and multi-process service (MPS)—primarily introduced to improve the programmability and efficiency of GPU kernels have an unexpected consequence—that of creating a novel covert timing channel via the GPUs translation lookaside buffer (TLB) hierarchy. To enable this covert channel, we first perform experiments to understand the characteristics of TLBs present on a GPU. The use of UVM allows fine-grained management of translations, and helps us discover several idiosyncrasies of the TLB hierarchy, such as three-levels of TLB, coalesced entries. We use this newly-acquired understanding to demonstrate a novel covert channel via the shared TLB. We then leverage MPS to increase the bandwidth of this channel by 40×. Finally, we demonstrate the channels utility by leaking data from a GPU-accelerated database application.
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DTSTART:20210609T120000Z
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