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UID:fe478a4e02d4935bcaf9fa8556d7b311-491
DTSTAMP:19700101T120011Z
DESCRIPTION:An MLIR-based High-level Synthesis Compiler for Hardware Accelerator Design
URL;VALUE=URI:https://www.csa.iisc.ac.in/newweb/event/491/an-mlir-based-high-level-synthesis-compiler-for-hardware-accelerator-design/
SUMMARY:The emergence of machine learning, image and audio processing on edge devices
has motivated research towards power-efficient custom hardware accelerators.
Though FPGAs are an ideal target for custom accelerators, the difficulty of
hardware design and the lack of vendor-agnostic, standardized hardware
compilation infrastructure has hindered their adoption.
High-level synthesis (HLS) offers a more compiler-centric alternative to the
traditional Verilog-based hardware design improving developer productivity.

In this work, we propose an MLIR-based end-to-end HLS compiler and an
an intermediate representation that is suitable for the design and implementation of
domain-specific accelerators for affine workloads. Our compiler brings similar
levels of modularity and extensibility to the HLS compilation domain, which
LLVM brought to the area of a software compilation.
A modular compiler infrastructure offers the advantage of incrementally
introducing new language frontends and optimization passes without the need to
reinvent the whole HLS compiler stack.

Our compiler converts a high-level description of the accelerator specified in
the C programming language into a register-transfer-level design
in SystemVerilog. We use memory dependence analysis and
integer-linear-program(ILP) based automatic scheduling on improving loop-pipelining and 
introduce parallelization between producer-consumer kernels.
Our ILP-based optimizer beats the state-of-the-art Vitis HLS compiler by 1.3x
in performance over a representative set of benchmarks while requiring fewer
FPGA resources.

Microsoft teams link:

https://teams.microsoft.com/l/meetup-join/19%3ameeting_MmVlOTllMzMtMWU2ZC00ZmQ2LWFmMDYtNDRkMjgxMDE5OTI2%40thread.v2/0?context=%7b%22Tid%22%3a%226f15cd97-f6a7-41e3-b2c5-ad4193976476%22%2c%22Oid%22%3a%22171d9abc-cf43-429a-9680-c05b9523fa9a%22%7d
DTSTART:20230727T120000Z
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