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UID:58239ac7375c6efc7df1838482d8a8c0-492
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DESCRIPTION:Data-Aware Network-on-Chip for High End Computing Systems
URL;VALUE=URI:https://www.csa.iisc.ac.in/newweb/event/492/data-aware-network-on-chip-for-high-end-computing-systems/
SUMMARY:Tiled Chip Multi-Processors (TCMP) is one of variant of  Multiprocessor System on Chips (MPSoCs) MPSoC  that  uses  Network  on  Chip  (NoC)  for  inter  tile communication. NoC is a multi-hop packet-based communication infrastructure that connects different cores with each other through routers. NoC provides a high transfer bandwidth, and the infrastructure is scalable.  Applications running on different cores access on-chip last level cache memories and off-chip main memory through the underlying NoC. As NoC plays a vital role in memory access latency, ignoring the nature of its infrastructure may severely impact the performance of the applications in TCMPs. This talk attempts to share some thoughts on a few architectural optimizations done to establish a dynamic cooperation between NoC and the memory hierarchy for improved performance. By gathering information about the data travelling from one level of memory to another, we exploit underutilized NoC resources to design techniques and propose optimizations that reduce memory access latency and improve overall system performance.
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