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UID:fc73000c6170c4ca036d86d0297b5742-97
DTSTAMP:19700101T120018Z
DESCRIPTION:Accelerator-level Parallelism
URL;VALUE=URI:https://www.csa.iisc.ac.in/newweb/event/97/accelerator-level-parallelism/
SUMMARY:Computer system performance has improved due to creatively using more transistors (Moore's Law) in parallel via bit-, instruction-, thread-, and data-level parallelism. With the slowing of technology scaling, a way to further improve computer system performance under energy constraints is to employ hardware accelerators. Each accelerator is a hardware component that executes a targeted computation class faster and usually with (much) less energy. Already today, many chips in mobile, edge and cloud computing concurrently employ multiple accelerators in what we call accelerator-level parallelism (ALP).
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This talk develops our hypothesis that ALP will spread to computer systems more broadly. ALP is a promising way to dramatically improve power-performance to enable broad, future use of deep Al, virtual reality, self-driving cars, etc. To this end, we review past parallelism levels and the ALP already present in mobile systems on a chip (SoCs). We then aid understanding of ALP with the Gables model and charge computer science researchers to develop better ALP "best practices" for: targeting accelerators, managing accelerator concurrency, choreographing inter-accelerator communication, and productively programming accelerators. This joint work with Vijay Janapa Reddi of Harvard. See also: https://www.sigarch.org/accelerator-level-parallelism/.
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