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DTEND:20201009T120000Z
UID:5a42038243b5eccac06abfbb93ecef8b-98
DTSTAMP:19700101T120011Z
DESCRIPTION:Making Microarchitecture-impossible Possible for Performance and Security
URL;VALUE=URI:https://www.csa.iisc.ac.in/newweb/event/98/making-microarchitecture-impossible-possible-for-performance-and-security/
SUMMARY:Single-thread performance is the key to the performance of desktops, laptops, servers, and handheld devices. However, in recent years, the industry trend shows that improvements in single-thread performance are starting to saturate as Moore's law comes to an end, making it impossible to improve performance further. The talk will focus on making the impossible, possible through a bouquet of hardware prefetchers.
General purpose CPUs usually suffer from a backend bottleneck, where data prefetchers come into the picture to hide the memory latency.
Recent data prefetchers use monolithic and gigantic structures demanding 100s of KBs to improve application performance, making it impossible for the industry to adopt these ideas. Even after 30 years of prefetching research, commercial processors still use 30 years-old prefetchers. The talk will highlight a bouquet-based tiny prefetcher that outperforms all the data prefetchers proposed in the last 30 years.
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Finally, the talk will provide a top-level view on the security side of microarchitecture, highlighting some of the offensive and defensive sides that seem impossible. On the offensive side, the talk will highlight the DABANGG cache attack that works on noisy systems, and on the defensive side, the talk will touch upon a lightweight and secure memory hierarchy for Trusted Execution Environments (TEEs).
DTSTART:20201009T120000Z
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