RESUME

Name: 		 		 Deepak D'Souza 




Date of birth: 		 		 14th June 1970 




Postal address: 		 		 Dept. of Computer Science & Automation, 


Indian Institute of Science, 


Bangalore 560 012. 




Residence: 		 		22/10 Vittal Mallya Road, 


Bangalore 560 001, India. 




Phone: 		 		 (+91-80) 2293 2468 (Off), 22933142 (direct) 


2360 2911 (Fax), 


2221 9759, 51120422 (Res) 




Email: 		 		 deepakd@csa.iisc.ernet.in 

EDUCATIONAL BACKGROUND

1. 1994-2000: Ph.D. (Computer Science), Chennai Mathematical Institute (Degree awarded by Birla Institute of Technology and Science, Pilani).

2. 1991-94: Masters in Computer Applications (M.C.A.)
   Department of Computer Science, University of Poona.

3. 1988-91: B.A. (Hons.) Mathematics,
   St. Stephen's College, Delhi University.

CURRENT POSITION

Since Oct 2003: Assistant Professor, Dept. of Computer Science & Automation, Indian Institute of Science, Bangalore.

PREVIOUS EXPERIENCE

1. Jan-Oct 2003: Visiting Scientist, Dept of Computer Science & Automation, Indian Institute of Science, Bangalore.

2. Nov 2000-Dec 2002: Fellow, Chennai Mathematical Institute.

3. Jan-Sep 2000: Post-doctoral Fellow,
   Chennai Mathematical Institute.

4. Jul-Sep 1994: Systems Engineer,
   Wipro Systems Ltd., Bangalore.

5. May-Dec 1993: Industrial Trainee,
   Business Systems Group, Lipton India Ltd., Bangalore.

6. May-Jul 1992: Summer Trainee,
   Altos India Ltd, New Delhi.

LONG TERM ACADEMIC VISITS

1. June-July 2004 and Sep-Oct 2001: As Visiting Associate Professor to Laboratory for Specification and Verification (LSV), Ecole Normale Superieure, Cachan, France.

2. Jun-Jul 1999: As Visiting PhD Student to BRICS, Department of Computer Science, Aarhus University, Denmark.

COLLABORATION WITH INDUSTRY

During 2001-02 I have worked on a joint project between CMI and the Tata Research Development and Design Centre (TRDDC). As part of this project we developed solutions for automatic test-case generation, and verifying consistency of SDL models with user-specified scenarios.

RESEARCH INTERESTS

• Automated verification.

• Temporal and real-time logics.

• Automated controller synthesis.

• Verifying security protocols

COURSES TAUGHT

1. Introduction to Programming (for Ist year Undergraduate students at CMI) Fall semester, 2000 and 2002.

2. Theory of Programming Languages (with Kamal Lodaya, IMSc) (for Ist year Ph.D. students) Fall semester, 2000.

3. Computer Organisation (for IInd year undergraduates), Spring semester 2001, and 2002.

4. Automated Verification, Spring Semester 2003, 2004 and 2005, at CSA Department, IISc, Bangalore.

5. Theory of Computation, Autumn Semester 2003, at CSA, IISc.

6. Mathematical Logic, Autumn Semester 2004, at CSA.

PUBLICATIONS

Journal articles

1. An Automata-Theoretic Approach to Constraint LTL, (with Stéphane Demri) submitted to Information and Computation (2003).

2. A Logical Characterisation of Event Clock Automata, in Intl. Journal of Foundations of Computer Science, Vol. 14, No. 4, World Scientific (2003).

3. Product Interval Automata, (with P. S. Thiagarajan) in Sadhana, Academy Proceedings in Engineering Sciences, 27, 2, Indian Academy of Sciences (2002), 181-208.

Conference articles

1. An automata-based approach to verifying information flow properties (with K R Raghavendra and Barbara Sprick) to appear in Proc. ARSPA Workshop 2005.

2. Fault diagnosis using timed automata (with Patricia Bouyer and Fabrice Chevalier) in Proc. FOSSACS 2005.

3. On timed automata with input-determined guards (with Nicolas Tabareau), in Joint conference of FORMATS/FTRTFT, Grenoble, France, LNCS 3253 (2004).

4. Timed control with partial observability (with Patricia Bouyer, P. Madhusudan, and Antoine Petit), in Proc. 15th Conf. on Computer Aided Verification (CAV 2003) LNCS 2725 (2003).

5. Checking consistency of SDL+MSC specifications (with Madhavan Mukund), in Proc. 10th International SPIN Workshop on Model Checking of Software (SPIN 2003) LNCS 2648 (2003).

6. An Automata-Theoretic Approach to Constraint LTL, (with Stéphane Demri) in Proc. 22nd Foundations of Software Technology and Theoretical Computer Science (FSTTCS) LNCS 2256 (2002).

7. Timed control synthesis for external specifications, (with P. Madhusudan) in Proc. 19th Symposium on Theoretical Aspects of Computer Science (STACS) 2002, LNCS 2285 (2002).

8. A Logical Characterisation of Event Recording Automata, in Proc. International Symposium on Formal Methods in Real-Time and Fault Tolerance (FTRTFT) 2000, LNCS 1926 (2000).

9. Product Interval Automata: A Subclass of Timed Automata, (with P. S. Thiagarajan), in Proc. 19th Foundations of Software Technology and Theoretical Computer Science (FSTTCS), LNCS 1732 (1999).

10. On-the-fly Verification for Product-LTL, (with P. Madhusudan) in Proc. Seventh National Seminar in Theoretical Computer Science, Chennai. (1997).

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