Graduated Students
- Jayvant Anantpur, Enhancing GPGPU Performance through Warp Scheduling, Divergence Taming and Runtime Parallelizing Transformations, May 2017.
- Nagendra Gulur Dwarakanath, Multi-Core Memory System Design: Developing and Using Analytical Models for Performance Evaluation and Enhancements, Aug. 2015. (jointly with Dr. Mahesh Mehendale (Texas Instruments)
- Sreepathi Pai, Efficient Dynamic Automatic Memory Management and Concurrent Kernel Execution for General-Purpose Programs on Graphics Processing Units, Nov. 2014. (jointly with
Prof. Matthew Jacob)
- R. Manikantan, Improving Last-Level Cache Performance in Single and Multi-Core Processors, Oct. 2013.
- Rupesh Nasre, Scaling Context-Sensitive Points-to Analaysis, Feb. 2012.
- Sandya S. Mannarswamy,,
Compiler Transformations for Improving the Performance of Software Transactional Memory, Nov. 2011. (jointly with
Dr. R. Badrinath, HP IESL, Bangalore)
- T.S. Rajesh Kumar,
On-Chip Memory Architecture Exploration of Embedded System on Chip, Sep. 2008. (jointly with
Dr. C.P. Ravikumar, Texas Instruments India Pvt. Ltd., Bangalore)
- Kaushik Rajan,
Efficient Cache Organization for Application Specific and General Purpose Processors,
May 2008.
- V. Santhosh Kumar,
Improving the Communication Performance of I/O Intensive and Communication Intensive Application
in Cluster Computer Systems, Oct. 2006. (jointly with Prof. Matthew Jacob)
- Adarsh Patil, Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Architectures, July 2017.
- Vaivaswatha N, Fast Flow-Sensitive Pointer Analysis, Aug. 2014.
- Prasanna Pandit, Cooperative Execution of OpenCL Programs on Multiple Heterogenous Devices, Nov. 2013
- Ashwin Prasad, Automatic Compilation of MATLAB Programs for Synergistic Execution on Heterogeneous Processors, Jan. 2012
- Abhishek Udupa,,
Efficient Compilation of Stream Programs for Multicores with Accelerators, July 2009.
- Aditya Thakur,,
Comprehensive Path-sensitive Data-flow Analysis, Aug. 2008.
- Girish B.C.,,
Efficient Techniques Exploiting Memory Hierarchy to Improve Network Processor Performance , Feb. 2008.
- Santosh G. Nagarakatte,,
Spill Code Minimization and Buffer and Code Size Aware Instruction Scheduling Techniques , Aug. 2007.
- Rajesh Vivekanandham,,
Scalable Low Power Issue Queue and Store Queue Design for Superscalar Processors , Dec. 2006.
- Sudhakar Surendran ,
A Systematic Approach to Synthesis of Verification Test-suites for
Modular SoC Designs , Nov. 2006. (jointly with Dr. Rubin Parekhji (Texas Instruments India))
- Govind S.,,
Performance Modeling and Evaluation of Network Processors , July 2006.
- K. Shyam,
Power-Aware Compilation Techniques for Embedded Systems , July 2006.
(jointly with Dr. Milind S. Gandhe (Sasken Corp.))
- Sarvani V.V.N.S.,
Compiler Techniques for Code Size and Power Reduction for Embedded
Processors , June 2004.
- A. Radhika Sarma ,
A Simple Replacement Policy and a Dynamic Prefetching Technique for WWW
Cache Processors , April 2004.
- Subash Chandar G.,
Reconfigurable Architectures for Application Specific Processors used in
Embedded Control Applications, Feb. 2002. (jointly with Dr. Mahesh Mehendale (Texas Instruments India))
- K.V. Manjunath,
Performance Analysis of Methods that Overcome False Sharing Effects in
Software DSMs, Apr. 2001.
- N.P. Manoj,
CAS-DSM: A Compiler Assisted Software Distributed Shared Memory System,
Apr. 1999.
- V. Janaki Ramanan,
Efficient Resource Usage Modelling, Apr. 1999.
- V. Sricharan, Study
of Cache and TLB Performance in a Distributed Virtual Shared Memory
System, April 1999.
- Madhavi G. Valluri,
Evaluation of Register Allocation and Instruction Scheduling Methods in
Multiple Issue Processors, Jan. 1999.
- Shivam Gupta, Analytical Model to Evaluate the Performance of GPU using a Two-Tier Regression-Based Design Space Exploration, M.E., Dec. 2017.
- Abhinav Anil Sharma, A Hybrid Model for Predicting Performance in
Heterogeneous System Architecture, M.E., June 2017.
- Patel Arth Kaushebhai, Improving Memory Hierarchy Performance in Heterogeneous System Architecture (HSA), M.E., June 2015.
- M. Aravind Krishnan, Large Graph Applications on GPUs, M.Tech., June 2012.
- T. Vasu Babu, Incorporating Dynamic Rate Support in StreamIt, M.E., June 2009.
- R. Karthikeyan,
A Multi-stage Linear Regression Strategy for Determining Rmax of a TOP500 System, M.Tech., July 2008.
(jointly with Dr. Sathish Vadhiyar)
- R. Manikantan, Performance Enhancement Schemes for Superscalar Processors: Ex
ploiting Narrow Width Results and Limited Prefetching, M.E., June 2006
- Rajani Pai, FEADS: A Framework for Exploring the Application Design Space on
Network Processors, M.E., June 2005
- Dushyant M.P. Enhancing the Performance of Clustered Superscalar Processors, M.E., June 2005
- S. Sujatha, A Clustered Digital Library Server with Cooperative
Semantic Cache, M.Tech., Jan. 2002.
- Anand Chitipothu, DOMP: OpenMP Programming on Cluster of SMPs, M.Tech., Jan.
2002.
- Vinodh Kumar R. Dynamic Path Profile Aided Recompilation in a Java
Just-In-Time Compiler, M.E., Jan. 2001.
- S.M. Sandhya, Instruction Scheduling Techniques in SUIF for Value
Speculation, M.E., Jan. 2000.
- Amit H. Rangari, Implementation of Simple COMA Simulator on R-SIM, M.E.,
Jan. 2000
- Veeral P. Shah, Copy Propagation Optimization and Linear Scan Register
Allocation in JIT Compilation, M.E., M.E., Jan. 2000.
- Srinivasan R., Compiler Optimizations in the Presence of Value
Speculation, M.E.(Int), July 1999.
- N. Sreraman, A Vectorizing Compiler for Exploiting Multimedia
Extensions, M.E.(Int), July 1999.
- V. Amar Nath, Performance Enhancement of Software Disributed Shared
Memory, M.E., Jan. 1999.
- V. Kumar, Java Virtual Machine: Just-in-Time Compiler Implementation
for SPARC, M.E., Jan. 1999
- P.S. Udaya Shankara, Granularity Study and Evaluation of Performance
Metrics for Shared Memory Accesses in Distributed Shared Memory Architectures
, M.E., Jan. 1999.
- R. Lakshmi, Performance Enhancement and Evaluation of DSM-SP2: A
Distributed Shared Memory, M.E.(Int), July 1997.
- B. Hari Krishna, Enhancing the Performance of Multithreaded
Architectures, M.E., Jan. 1997.
- N.S.S. Narasimha Rao, Implementation of Three Software Pipelining
Methods, M.E., Jan. 1997.
- S. Ramesh, DSM-SP2: An Implementation of Distributed Shared Memory on
IBM SP2, M.E., Jan. 1997.
- Biren Gandhi, Distributed Shared Memory on Network of Workstations with
TCP/IP, M.E., Jan. 1997.
- Amod K. Dani, Software Pipelining for VLIW Architectures , M.E., Jan.
1997.