{"id":30,"date":"2026-06-11T12:40:31","date_gmt":"2026-06-11T07:10:31","guid":{"rendered":"https:\/\/surfzone.in\/iisc-csa-udayb\/wp\/?page_id=30"},"modified":"2026-08-13T11:05:38","modified_gmt":"2026-08-13T05:35:38","slug":"research-all","status":"publish","type":"page","link":"https:\/\/www.csa.iisc.ac.in\/~udayb\/research-all\/","title":{"rendered":"Research"},"content":{"rendered":"\n<p>My interests are in the design of compilers, programming models, and runtimes for high-performance Artificial Intelligence (AI) systems powered by multicores and accelerators, with an emphasis on automatic parallelization and high performance. Computational domains of particular interest to me include stencil computations, image processing pipelines, dense linear algebra, and deep learning.<\/p>\n\n\n<style>.kt-tabs-id30_9faaf4-ac > .kt-tabs-content-wrap > .wp-block-kadence-tab{border-top:1px solid var(--global-palette7, #eeeeee);border-right:0px solid var(--global-palette7, #eeeeee);border-bottom:0px solid var(--global-palette7, #eeeeee);border-left:0px solid var(--global-palette7, #eeeeee);border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;padding-top:var(--global-kb-spacing-sm, 1.5rem);padding-right:var(--global-kb-spacing-sm, 1.5rem);padding-bottom:var(--global-kb-spacing-sm, 1.5rem);padding-left:var(--global-kb-spacing-sm, 1.5rem);background:var(--global-palette9, #ffffff);}.wp-block-kadence-tabs .kt-tabs-id30_9faaf4-ac > .kt-tabs-title-list li{margin-top:0px;margin-right:8px;margin-bottom:0px;margin-left:0px;}.wp-block-kadence-tabs .kt-tabs-id30_9faaf4-ac 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.kt-tab-inner-content{margin-top:0px;margin-right:8px;margin-bottom:0px;margin-left:0px;}.wp-block-kadence-tabs .kt-tabs-id30_9faaf4-ac > .kt-tabs-title-list li .kt-tab-title:hover, .wp-block-kadence-tabs .kt-tabs-id30_9faaf4-ac > .kt-tabs-content-wrap > .kt-tabs-accordion-title .kt-tab-title:hover{border-color:var(--global-palette7, #eeeeee);color:#000000;background:var(--global-palette9, #ffffff);}.wp-block-kadence-tabs .kt-tabs-id30_9faaf4-ac > .kt-tabs-title-list li.kt-tab-title-active .kt-tab-title, .wp-block-kadence-tabs .kt-tabs-id30_9faaf4-ac > .kt-tabs-content-wrap > .kt-tabs-accordion-title.kt-tab-title-active .kt-tab-title{border-color:#fcb900;color:#000000;background:var(--global-palette9, #ffffff);}@media all and (max-width: 1024px), only screen and (min-device-width: 1024px) and (max-device-width: 1366px) and (-webkit-min-device-pixel-ratio: 1.5) and (orientation: landscape){.kt-tabs-id30_9faaf4-ac > .kt-tabs-content-wrap > .wp-block-kadence-tab{border-top:1px solid var(--global-palette7, #eeeeee);border-right:0px solid var(--global-palette7, #eeeeee);border-bottom:0px solid var(--global-palette7, #eeeeee);border-left:0px solid var(--global-palette7, #eeeeee);}}@media all and (max-width: 767px){.kt-tabs-id30_9faaf4-ac > .kt-tabs-content-wrap > .wp-block-kadence-tab{border-top:1px solid var(--global-palette7, #eeeeee);border-right:0px solid var(--global-palette7, #eeeeee);border-bottom:0px solid var(--global-palette7, #eeeeee);border-left:0px solid var(--global-palette7, #eeeeee);}}<\/style>\n<div class=\"wp-block-kadence-tabs alignnone\"><div class=\"kt-tabs-wrap kt-tabs-id30_9faaf4-ac kt-tabs-has-3-tabs kt-active-tab-1 kt-tabs-layout-tabs kt-tabs-tablet-layout-inherit kt-tabs-mobile-layout-inherit kt-tab-alignment-left \"><ul class=\"kt-tabs-title-list\"><li id=\"tab-publications\" class=\"kt-title-item kt-title-item-1 kt-tabs-svg-show-always kt-tabs-icon-side-right kt-tab-title-active\"><a href=\"#tab-publications\" data-tab=\"1\" class=\"kt-tab-title kt-tab-title-1 \"><span class=\"kt-title-text\">Publications<\/span><\/a><\/li><li id=\"tab-researchreports\" class=\"kt-title-item kt-title-item-2 kt-tabs-svg-show-always kt-tabs-icon-side-right kt-tab-title-inactive\"><a href=\"#tab-researchreports\" data-tab=\"2\" class=\"kt-tab-title kt-tab-title-2 \"><span class=\"kt-title-text\">Research Reports<\/span><\/a><\/li><li id=\"tab-phdthesis\" class=\"kt-title-item kt-title-item-3 kt-tabs-svg-show-always kt-tabs-icon-side-right kt-tab-title-inactive\"><a href=\"#tab-phdthesis\" data-tab=\"3\" class=\"kt-tab-title kt-tab-title-3 \"><span class=\"kt-title-text\">Ph.D. Thesis<\/span><\/a><\/li><\/ul><div class=\"kt-tabs-content-wrap\">\n<div class=\"wp-block-kadence-tab kt-tab-inner-content kt-inner-tab-1 kt-inner-tab30_b9caa0-02\"><div class=\"kt-tab-inner-content-inner\">\n<p><em><a href=\"http:\/\/scholar.google.co.in\/citations?hl=en&amp;user=cwo0elIAAAAJ&amp;oi=sra\" target=\"_blank\" rel=\"noreferrer noopener\">Google scholar profile<\/a><\/em>, <em><a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/b\/Bondhugula:Uday\" target=\"_blank\" rel=\"noreferrer noopener\">DBLP<\/a><\/em>, <em><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday.bib\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday.bib\" target=\"_blank\" rel=\"noreferrer noopener\">BibTeX<\/a><\/em><\/p>\n\n\n\n<ol id=\"list\" class=\"wp-block-list\">\n<li><a href=\"https:\/\/arxiv.org\/abs\/2603.06731\">PolyBlocks: A Compiler Infrastructure for AI Chips and Programming Frameworks<\/a><br>Uday Bondhugula, Akshay Baviskar, Navdeep Katel, Vimal Patel, Anoop JS, and Arnab Dutta.<br><em>arXiv:2603.06731, Mar 2026.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3694715.3695958\">SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference<\/a><br>Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R Govindarajan, and Uday Bondhugula.<br><em>ACM Symposium on Operating Systems Principles (SOSP), 2024<\/em>.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3623278.3624767\">HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description<\/a><br>Kingshuk Majumder and Uday Bondhugula<br><em>ASPLOS 2023<\/em>.<br><\/li>\n\n\n\n<li>Treebeard: An Optimizing Compiler for Decision Tree-Based ML Inference<br>Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R Govindarajan, Uday Bondhugula.<br><em>IEEE\/ACM International Symposium on Microarchitectures (MICRO), Oct 2022.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3497776.3517770\">MLIR-Based Code Generation for GPU Tensor Cores<\/a><br>Navdeep Katel, Vivek Khandelwal, and Uday Bondhugula.<br><em>ACM\/IEEE International conference on Compiler Construction (CC), Apr 2022.<\/em><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3447818.3462213\">A Practical Tile Size Selection Model for Affine Loop Nests<\/a><br>Kumudha Narasimhan, Aravind Acharya, Abhinav Baid, and Uday Bondhugula.<br><em>ACM International Conference on Supercomputing (ICS&#8217;21), Jun 2021.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/doi\/10.1109\/CGO51591.2021.9370308\">MLIR: Scaling Compiler Infrastructure for Domain-Specific Computation<\/a><br>Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, and Oleksandr Zinenko.<br><em>ACM International Symposium on Code Generation and Optimization (CGO), 12 pages, Feb 2021.<\/em><br><\/li>\n\n\n\n<li>Effective Loop Fusion in Polyhedral Compilation using Fusion Conflict Graphs<br>Aravind Acharya, Uday Bondhugula, Albert Cohen.<br><em>ACM Transactions on Architecture and Code Optimization (TACO), vol 17, issue 4, article no. 26, Sep 2020.<\/em><br><\/li>\n\n\n\n<li>Optimizing the Linear Fascicle Evaluation Algorithm for Multi-Core and Many-Core Systems<br>Karan Aggarwal and Uday Bondhugula<br><em>ACM Transactions on Parallel Computing, vol 7, number 4, article no. 22, Nov 2020.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/doi\/10.1109\/CGO51591.2021.9370308\">An Effective Fusion and Tile Size Model for PolyMage<\/a><br>Abhinav Jangda and Uday Bondhugula<br><em>ACM Transactions on Programming Languages and Systems (TOPLAS), vol 42, issue 3, article no. 12, 27 pages, Nov 2020.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3377555.3377899\">Bitwidth Customization in Image Processing Pipelines using Interval Analysis and SMT Solvers<\/a><br>Suresh Purini, Vinamra Benara, Ziaul Chowdhury, Uday Bondhugula.<br><em>ACM SIGPLAN International Conference on Compiler Construction (CC), pages 167-178, Feb 2020.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/citation.cfm?id=3332469\">Optimizing the Linear Fascicle Evaluation Algorithm for Many-Core Systems<\/a><br>Karan Aggarwal, Uday Bondhugula<br><em>International Conference on Supercomputing (ICS), Jun 2019.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/authorize?N678297\">Polyhedral Auto-Transformation with No Integer Linear Programming<\/a><br>Aravind Acharya, Uday Bondhugula, Albert Cohen<br><em>ACM SIGPLAN PLDI, Jun 2018.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/citation.cfm?id=3178507\">An Effective Fusion and Tile Size Model for Optimizing Image Processing Pipelines<\/a><br>Abhinav Jangda, Uday Bondhugula<br><em>ACM SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP), Feb 2018<\/em>.<br>Artifact evaluated (reusable and <a href=\"https:\/\/bitbucket.org\/udayb\/polymage\/branch\/ppopp-2018-ae\">available<\/a>).<br><\/li>\n\n\n\n<li>Optimizing Geometric Multigrid Method Computation using a DSL Approach [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/slides\/multigrid-polymage.pdf\">slides<\/a>, <a href=\"https:\/\/bitbucket.org\/udayb\/polymage\/src\/a0665203bb764faea9c05c2d76f2e8662985e555\/sandbox\/apps\/python\/multigrid\/?at=master\">benchmarks<\/a>]<br>Vinay Vasista, Kumudha KN, Siddharth Bhat, Uday Bondhugula<br><em>Supercomputing (SC), Nov 2017.<\/em><br><\/li>\n\n\n\n<li id=\"diamond-tiling\"><a href=\"http:\/\/ieeexplore.ieee.org\/document\/7582549\/\">Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations<\/a><br>Uday Bondhugula, Vinayaka Bandishti, Irshad Pananilath<br><em>IEEE Transactions on Parallel and Distributed Systems (TPDS), pg 1285-1298, Vol 28, Issue 5, May 2017.<br>(extended version of SC&#8217;12 paper)<\/em><br><\/li>\n\n\n\n<li><a href=\"http:\/\/dl.acm.org\/authorize?N12726\">A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs<\/a><br>Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula<br><em>IEEE International conference on Parallel Architectures and Compilation Techniques (PACT 2016), Sep 2016.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/authorize?N19655\">Compiling Affine Loop Nests for a Dynamic Scheduling Runtime on Shared and Distributed Memory<\/a><br>Roshan Dathathri, Ravi Teja Mullapudi, Uday Bondhugula<br><em>ACM Transactions on Parallel Computing (TOPC), vol 3, issue 2, Jul 2016.<\/em><br><\/li>\n\n\n\n<li><a href=\"http:\/\/dl.acm.org\/authorize?N19658\">SMO: An Integrated Approach to Intra-Array and Inter-Array Storage Optimization [PDF<\/a>, <a href=\"http:\/\/hicaps.csa.iisc.ac.in\/smo.html\">Tool]<\/a><br>Somashekaracharya Bhaskaracharya, Uday Bondhugula, Albert Cohen<br><em>ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL), Jan 2016<\/em>.<br><\/li>\n\n\n\n<li><a href=\"http:\/\/dl.acm.org\/authorize?N19657\">Automatic Storage Optimization for Arrays<\/a> [<a href=\"http:\/\/hicaps.csa.iisc.ac.in\/smo.html\">Tool<\/a>]<br>Somashekaracharya Bhaskaracharya, Uday Bondhugula, Albert Cohen<br><em>ACM Transactions on Programming Languages and Systems (TOPLAS), vol 38, issue 3, Apr 2016.<\/em><br><em>Selected for presentation at ACM SIGPLAN PLDI&#8217;16, Jun 2016.<\/em><br><\/li>\n\n\n\n<li><a href=\"http:\/\/dl.acm.org\/authorize?N19656\">The Pluto+ Algorithm: A Practical Approach for Parallelization and Locality Optimization of Affine Loop Nests [PDF]<\/a><br>Uday Bondhugula, Aravind Acharya, Albert Cohen<br><em>ACM Transactions on Programming Languages and Systems (TOPLAS), vol 38, issue 3, Apr 2016.<\/em><br><\/li>\n\n\n\n<li>An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations [<a href=\"http:\/\/dl.acm.org\/authorize?N07021\">PDF<\/a>, <a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-lbm-talk.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-lbm-talk.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">slides<\/a>]<br>Irshad Pananilath, Aravind Acharya, Vinay Vasista, Uday Bondhugula<br><em>ACM Transactions on Architecture and Code Optimization (TACO), volume 12, issue 2, article 14, July 2015.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/authorize?N30039\">PolyMage: Automatic Optimization for Image Processing Pipelines [PDF]<\/a><br><a href=\"http:\/\/dl.acm.org\/author_page.cfm?id=94658611998\">Ravi Teja Mullapudi<\/a>, <a href=\"http:\/\/dl.acm.org\/author_page.cfm?id=94658609188\">Vinay Vasista<\/a>, <a href=\"http:\/\/dl.acm.org\/author_page.cfm?id=81326487775\">Uday Bondhugula<\/a><br><em>ASPLOS &#8217;15: International Conference on Architectural Support for Programming Languages and Operating Systems, Mar 2015.<\/em><br><\/li>\n\n\n\n<li>PLUTO+: Near-Complete Modeling of Affine Transformations for Parallelism and Locality [<a href=\"http:\/\/dl.acm.org\/authorize?N30030\">PDF<\/a>]<br>Aravind Acharya, Uday Bondhugula<br><em>ACM SIGPLAN symposium on Principle and Practice of Parallel Programming (PPoPP), Feb 2015.<\/em><br><\/li>\n\n\n\n<li>Tiling and Optimizing Time-Iterated Computations over Periodic Domains [<a href=\"https:\/\/dl.acm.org\/authorize?N678298\">PDF<\/a>, <a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact14-talk.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact14-talk.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">slides<\/a>, <a href=\"http:\/\/hicaps.csa.iisc.ac.in\/downloads\/periodic-stencil-pact14-codes-0.1.0.tar.gz\">code<\/a>]<br>Uday Bondhugula, Vinayaka Bandishti, Albert Cohen, Guillain Potron, Nicolas Vasilache<br><em>IEEE International conference on Parallel Architectures and Compilation Techniques (PACT 2014), Aug 2014.<\/em><br><strong><em>Nominated for the best paper award.<\/em><\/strong><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/authorize?N678299\">Effective automatic computation placement and data allocation for parallelization of regular programs<\/a><br>Chandan Reddy, Uday Bondhugula<br><em>ICS &#8217;14 Proceedings of the 28th ACM international conference on Supercomputing, Jun 2014.<\/em><br><\/li>\n\n\n\n<li><a href=\"http:\/\/dl.acm.org\/authorize?6963812\">Automatic data allocation and buffer management for multi-GPU machines<\/a><br>Thejas Ramashekar, Uday Bondhugula<br><em>ACM Transactions on Architecture and Code Optimization (TACO), Vol 10, No. 4, Article 60, Dec 2013.<\/em><br><\/li>\n\n\n\n<li>Compiling Affine Loop Nests for Distributed-Memory Parallel Architectures [<a href=\"http:\/\/dl.acm.org\/citation.cfm?id=2503289\">PDF<\/a>, <a href=\"https:\/\/github.com\/bondhugula\/pluto\/tree\/distmem\">tool<\/a>, <a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-sc13-slides-1.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-sc13-slides-1.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">slides<\/a>]<br>Uday Bondhugula<br><em>ACM\/IEEE Supercomputing (SC &#8217;13), Nov 2013, Denver, USA.<\/em><br><\/li>\n\n\n\n<li>Generating Efficient Data Movement Code for Heterogeneous Architectures with Distributed-Memory [<a href=\"http:\/\/dl.acm.org\/citation.cfm?id=2523771\">PDF<\/a>, <a href=\"http:\/\/repo.or.cz\/w\/pluto.git\/shortlog\/refs\/heads\/distmem\">Tool<\/a> ]<br>Roshan Dathathri, Chandan Reddy, Thejas Ramashekar, Uday Bondhugula<br><em>International conference on Parallel Architectures and Compilation Techniques (PACT 2013), Sep 2013, Edinburgh, UK.<\/em><br><\/li>\n\n\n\n<li>PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-cc13.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-cc13.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a> ]<br>Somashekar Bhaskaracharya, Uday Bondhugula<br><em>International conference on Compiler Construction (CC 2013), Mar 2013, Rome, Italy.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/citation.cfm?id=2389051\">Tiling Stencil Computations to Maximize Parallelism<\/a> [<a href=\"https:\/\/dl.acm.org\/citation.cfm?id=2389051\">PDF<\/a>, <a href=\"http:\/\/hicaps.csa.iisc.ac.in\/downloads\/stencil-codes\/\">code<\/a>, <a href=\"http:\/\/repo.or.cz\/w\/pluto.git\/shortlog\/refs\/heads\/diamond-tiling\">tool<\/a>]<br>Vinayak Bandishti, Irshad Pananilath, and Uday Bondhugula<br><em>ACM\/IEEE Supercomputing, Nov 2012, Utah, USA.<\/em><br><strong>Note:<\/strong> please refer to the <a href=\"#diamond-tiling\">journal extension<\/a> instead of this.<br><\/li>\n\n\n\n<li>Loop Transformations: Convexity, Pruning, and Optimization [<a href=\"http:\/\/dl.acm.org\/citation.cfm?id=1926449\">PDF<\/a>]<br>Louis-Noel Pouchet, Uday Bondhugula, Cedric Bastoul, Albert Cohen, J Ramanujam, P Sadayappan, and Nicolas Vasilache<br><em>ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages (POPL), Jan 2011, Austin, USA.<\/em><br><\/li>\n\n\n\n<li><a href=\"http:\/\/dl.acm.org\/citation.cfm?id=1884672\">Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework<\/a><br>Louis-Noel Pouchet, Uday Bondhugula, Cedric Bastoul, Albert Cohen, J Ramanujam, and P Sadayappan<br><em>Supercomputing (SC), 2010, New Orleans, USA.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact10.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact10.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">A Model for Fusion and Code Motion in an Integrated Auto-Parallelizing Compiler<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact10.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact10.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>Uday Bondhugula, Oktay Gunluk, Sanjeeb Dash, and L. Renganarayana<br><em>International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep 2010, Vienna, Austria.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-sc09.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-sc09.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Compact Multi-dimensional Kernel Extraction for Register Tiling<\/a><br>L. Renganarayana, Uday Bondhugula, Salem Derisavi, Alexandre E. Eichenberger, and Kevin O&#8217;Brien<br><em>Supercomputing (SC), 2009, Portland, USA.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp09.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp09.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Compiler-Assisted Dynamic Scheduling for Effective Parallelization of Loop Nests on Multicore Processors<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp09.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp09.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>M. Baskaran, N. Vydyanathan, Uday Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan.<br><em>ACM SIGPLAN Symposium on Principle and Practice of Parallel Programming (PPoPP), Feb 2009, Raleigh, North Carolina.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact09.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pact09.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Data Layout Transformation for Enhancing Locality on NUCA Chip Multiprocessors<\/a><br>Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, and Tin-fook Ngai.<br><em>International Conference on Parallel Architectures and Compilation Techniques (PACT), 2009, Raleigh, USA.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/dl.acm.org\/authorize?N20736\">A Practical Automatic Polyhedral Parallelizer and Locality Optimizer<\/a> [<a href=\"http:\/\/dl.acm.org\/authorize?N20736\">PDF<\/a>]<br>Uday Bondhugula, A. Hartono, J. Ramanujan, P. Sadayappan.<br><em>ACM SIGPLAN Programming Languages Design and Implementation (PLDI), Jun 2008, Tucson, Arizona, USA.<\/em><br><strong><em>ACM SIGPLAN Most Influential Paper Award in 2018.<\/em><\/strong><br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-cc08.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-cc08.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-cc08.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-cc08.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>Uday Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan.<br><em>International Conference on Compiler Construction (ETAPS CC), Apr 2008, Budapest, Hungary.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ics08.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ics08.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">A Compiler Framework for Optimization of Affine Loop Nests for GPGPUs<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ics08.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ics08.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>Muthu Baskaran, Uday Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan.<br><em>ACM International Conference on Supercomputing (ICS), Jun 2008, Island of Kos, Greece.<\/em><br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp08.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp08.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Automatic Data Movement and Computation Mapping for Multi-level Parallel Architectures with Explicitly Managed Memories<\/a>.<br>Muthu Baskaran, Uday Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan.<br><em>ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)<\/em>, Feb 2008, Salt Lake City, Utah.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pldi07.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pldi07.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Effective Automatic Parallelization of Stencil Computations<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pldi07.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-pldi07.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>S. Krishnamoorthy, M. Baskaran, Uday Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan.<br><em>ACM SIGPLAN Programming Language Design and Implementation (PLDI)<\/em>, Jun 2007, San Diego, California.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp07.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp07.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Automatic Mapping of Nested Loops to FPGAs<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp07.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ppopp07.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>Uday Bondhugula, J. Ramanujam, and P. Sadayappan.<br><em>ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)<\/em>, Mar 2007, San Jose, California.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-fccm06.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-fccm06.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Hardware\/Software Integration for FPGA-based All-Pairs Shortest-Paths<\/a> [ <a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-fccm06.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-fccm06.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>Uday Bondhugula, A. Devulapalli, James Dinan, J. Fernando, Pete Wyckoff, E. Stahlberg, and P. Sadayappan.<br><em>IEEE Symposium on Field-Programmable Custom Computing Machines (<a href=\"http:\/\/www.fccm.org\">FCCM &#8217;06<\/a>)<\/em>, Apr 2006, Napa Valley, California.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ipdps06.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ipdps06.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Parallel FPGA-based All-Pairs Shortest-Paths in a Directed Graph<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ipdps06.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ipdps06.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a> | <a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ipdps06-talk.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-ipdps06-talk.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">talk<\/a> | <a href=\"https:\/\/github.com\/bondhugula\/fw_fpga\">HDL code<\/a>]<br>Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, and P. Sadayappan.<br><em>20th IEEE International Parallel &amp; Distributed Processing Symposium (<a href=\"http:\/\/www.ipdps.org\">IPDPS &#8217;06<\/a>)<\/em>, Apr 2006, Rodos, Greece.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-rdma-allgather.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-rdma-allgather.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">High Performance RDMA-based All-to-all Broadcast for InfiniBand Clusters<\/a> [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-rdma-allgather.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-rdma-allgather.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>S. Sur, Uday Bondhugula, A. Mamidala, H.-W. Jin, and D. K. Panda.<br><em>12th IEEE International Conference on High Performance Computing (<a href=\"http:\/\/www.hipc.org\">HiPC &#8217;05<\/a>)<\/em>, Dec 2005, Bangalore, India.<\/li>\n<\/ol>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-kadence-tab kt-tab-inner-content kt-inner-tab-2 kt-inner-tab30_f02773-1c\"><div class=\"kt-tab-inner-content-inner\">\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/arxiv.org\/abs\/2002.11054\">MLIR: A Compiler Infrastructure for the End of Moore&#8217;s Law<\/a><br>Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, and Oleksandr Zinenko.<br><a href=\"https:\/\/arxiv.org\/abs\/2002.11054\">arXiv:2002.11054<\/a>, Feb 2020.<\/li>\n\n\n\n<li><a href=\"https:\/\/arxiv.org\/abs\/2003.00532\">High Performance Code Generation in MLIR: An Early Case Study with GEMM<\/a><br>Uday Bondhugula<br>arXiv preprint arXiv:2003.00532, Mar 2020.<\/li>\n\n\n\n<li>Automatic Intra-Array Storage Optimization [<a href=\"http:\/\/www.csa.iisc.ac.in\/TR\/2014\/3\/\">PDF<\/a>]<br>Somashekaracharya G Bhaskaracharya, Uday Bondhugula, Albert Cohen<br>IISc-CSA-TR-2014-3, Nov 2014.<\/li>\n\n\n\n<li>Handling Negative Coefficients in Automatic Transformation Schedules<br>Uday Bondhugula, Albert Cohen<br>Technical report, IISc-CSA-TR-1, Feb 2014.<br>Superseded by the Pluto+ paper at PPoPP&#8217;15 listed above.<\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday11distmem-tr.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday11distmem-tr.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Automatic Distributed Memory Code Generation using the Polyhedral Framework<\/a><br>Uday Bondhugula<br>IISc Research Report, IISc-CSA-TR-2011-3.<\/li>\n\n\n\n<li><a href=\"http:\/\/domino.watson.ibm.com\/library\/CyberDig.nsf\/1e4115aea78b6e7c85256b360066f0d4\/efe521ab23a0d28b85257784004dc9dd!OpenDocument&amp;,Bordawekar\">Can CPUs Match GPUs on Performance with Productivity?: Experiences with Optimizing a FLOP-intensive Application on CPUs and GPU<\/a><br>Rajesh Bordawekar, Uday Bondhugula, Ravi Rao<br><em>IBM Research Report RC25033, IBM T.J. Watson Research Center, Yorktown Heights, New York, Aug 2010.<\/em><\/li>\n\n\n\n<li><a href=\"http:\/\/domino.watson.ibm.com\/library\/CyberDig.nsf\/1e4115aea78b6e7c85256b360066f0d4\/9192e6536facfcef85257720005a0265!OpenDocument&amp;,bondhugula\">Believe it or Not! Multicore CPUs can Match GPUs for FLOP-intensive Applications!<\/a><br>Rajesh Bordawekar, Uday Bondhugula, Ravi Rao<br><em>IBM Research Report RC24982, IBM TJ Watson Research Center, Yorktown Heights, New York, Apr 2010.<\/em><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/tr70.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/tr70.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PLUTO: A Practical and Fully Automatic Polyhedral Program Optimization System<\/a><br>Uday Bondhugula, J. Ramanujam, and P. Sadayappan.<br><em>OSU Research Report OSU-CISRC-10\/07-TR70, Oct 2007.<\/em><\/li>\n\n\n\n<li><a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/tr43.pdf\" data-type=\"link\" data-id=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/tr43.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">Affine transformations for communication minimal parallelization and locality optimization of arbitrarily nested loop sequences<\/a><br>Uday Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan.<br><em>OSU Research Report OSU-CISRC-5\/07-TR43, May 2007.<\/em><\/li>\n<\/ul>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-kadence-tab kt-tab-inner-content kt-inner-tab-3 kt-inner-tab30_df8234-d6\"><div class=\"kt-tab-inner-content-inner\">\n<ul class=\"wp-block-list\">\n<li>Effective Automatic Parallelization and Locality Optimization using the Polyhedral Model [<a href=\"https:\/\/www.csa.iisc.ac.in\/~udayb\/wordpress\/wp-content\/uploads\/2026\/06\/uday-thesis.pdf\" target=\"_blank\" rel=\"noreferrer noopener\">PDF<\/a>]<br>Ph.D. thesis, Defended Aug 4th, 2008, The Ohio State University, USA.<\/li>\n<\/ul>\n<\/div><\/div>\n<\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"<p>My interests are in the design of compilers, programming models, and runtimes for high-performance Artificial Intelligence (AI) systems powered by multicores and accelerators, with an emphasis on automatic parallelization and high performance. Computational domains of particular interest to me include stencil computations, image processing pipelines, dense linear algebra, and deep learning.<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":2,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-30","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/pages\/30","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/comments?post=30"}],"version-history":[{"count":38,"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/pages\/30\/revisions"}],"predecessor-version":[{"id":413,"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/pages\/30\/revisions\/413"}],"wp:attachment":[{"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/media?parent=30"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/categories?post=30"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.csa.iisc.ac.in\/~udayb\/wp-json\/wp\/v2\/tags?post=30"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}