vaddr = c02c9458

1100 0000 0010 1100 1001 0100 0101 1000


PDPTE SELECTION

pdpi_index = (vaddr >> 30) * sizeof(uint64_t);

>> 30 = 0000 0000 0000 0000 0000 0000 0000 0011 = 3
sizeof(uint64_t) = 8
8*3 = 24 = 0x18

CR3 - 04f3f000

0000 0100 1111 0011 1111 0000 0000 0000

PDPTEi = addition of this an CR3

PDPTEi = 0x4f3f018

PDPTEi Value = 0x0000000004328001

If P flag, bit 0, of PDPTEi value is 0 there is no mapping in this 1 GB region.  Reference using
a linear address in this region causes a page-fault exception (section 4.7 Intel).

If the P flag of PDPTEi is 1, 4-KByte naturally aligned page directory is located at
the physical address specified in bits 51:12 of PDPTEi.  A page directory comprises 512 
64-bit entries (PDEs). A PDE is selected using the physical address defined as follows:




PDE SELECTION

Bits 51:12 are from PDPTEi:  000000000000   | 0000 0000 0000 0000 0000 0000 0100 0011 0010 1000 |     000000000001

Bits 11:3 are from 29:21 virt address: 110     |  0 0000 0010  |      1100 1001 0100 0101 1000

Bits 2:0 are 0

0000 0000 0000 0000 0000 0000 0100 0011 0010 1000 0000 0000 1000

PDE address = 0x0000004328008
PDE Value = 0x00000000615a3067

0000 0000 0000 0000 0000 0000 0000 0000 0110 0001 0101 1010 0011 0000 0110 0111

Use of the PDE value depends on the PS flag, bit 7.   - in this case it is 0

If the PDE’s PS flag is 1, the PDE maps a 2-MByte page.

If the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is located at the
physical address specified in bits 51:12 of the PDE (see Table 4-10). A page
directory comprises 512 64-bit entries (PTEs). A PTE is selected using the
physical address defined as follows:






PTE SELECTION

Bits 51:12 are from the PDE: 0000 0000 0000  |   0000 0000 0000 0000 0000 0110 0001 0101 1010 0011  |     0000 0110 0111

Bits 11:3 are bits 20:12 of the virt address:  1100 0000 001    |   0 1100 1001   |   0100 0101 1000

Bits 2:0 are 0

0000 0000 0000 0000 0000 0110 0001 0101 1010 0011 0110 0100 1000

PTE address = 0x00000615a3648
PTE Value: 0x00000000614a8023

0000 0000 0000 0000 0000 0000 0000 0000 0110 0001 0100 1010 1000 0000 0010 0011

Check bit 0 again for valid page in range like at first step

Because a PTE is identified using bits 31:12 of the linear address, every PTE maps
a 4-KByte page (see Table 4-11). The final physical address is computed as
follows:

FINDING THE PAGE

Bits 51:12 are from the PTE: 0000 0000 0000   |    0000 0000 0000 0000 0000 0110 0001 0100 1010 1000     |  0000 0010 0011

Bits 11:0 are from the original linear address: 1100 0000 0010 1100 1001 |  0100 0101 1000

0000 0000 0000 0000 0000 0110 0001 0100 1010 1000 0100 0101 1000

PAGE: 0x00000614a8458


dirty bit is located at bit 6 of the PTE