Space/time tradeoffs in code compression for the TMS320C62x processor
Sreejith Menon and Priti Shankar
IISc-CSA-TR-2004-4
(July 2004) Available formats: [pdf]
Filed on July 9, 2004
Updated on September 3, 2004
Reducing instruction memory requirements by improving code density using compression techniques has been the aim of much recent work on embedded devices. Previous work has been successful in improving compression ratios with modest decompression overhead for general purpose RISC architectures. However, most traditional compression techniques fail to produce good results for tightly encoded VLIW architectures. Increased popularity of highly flexible VLIW instruction formats have triggered a search for new variants of traditional compression schemes which achieve good compression ratios with low decompression overhead. We propose a simple variant of a dictionary based compression scheme and report the results of simulations on a widely used VLIW architecture, the TI TMS320C62x, exploring various options like field sizes, use of profiling information, and study their effects on compression ratios and decompression overheads. The advantage of our scheme is its simplicity and its easy adaptability to varying instruction formats.
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[Updated at 2009-10-22T06:42Z]