Applying Genetic Algorithms to Optimize Power in Tiled
SNUCA Chip Multicore Architectures
Aparna Mandke, Bharadwaj Amrutur & Y.N.Srikant
We propose a novel technique for reducing the power consumed by the
on-chip cache on SNUCA chip multicore platform. This is achieved by what we
call a ``remap table'', which maps accesses to the cache banks that are as
close as possible to the cores, on which the processes are scheduled. With this
technique, instead of using all the available cache, we use a portion of the
cache and allocate lesser cache to the application.
We formulate the problem as an energy-delay(ED) minimization problem and solve
it offline using a scalable genetic algorithm approach.
Our experiments show up to 40% of savings in the memory sub-system power
consumption and 47% savings in energy-delay product (ED).