Brief Biography

I am a project associate in the Department of Computer Science and Automation at IISc., Bangalore.

I completed my B.E in 2024 in Electronics and Communication Engineering at BITS-Pilani.

I wrote my undergraduate thesis at the FIST group, continuing my work after graduation.

My ongoing work involves constructing analytical models for calculating latency in a Network-on-Chip. It involves knowledge about computer and interconnect architecture, as well as queuing theory.

This work is relevant because with manycore systems gaining popularity, pre-silicon design space exploration of these systems face many challenges. Full system cycle-accurate simulations take a long time, and almost 90% of this can be spent just to simulate the interconnect. Analytical models cut down this time significantly.