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Data-Aware Network-on-Chip for High End Computing Systems

Series: Department Seminar

Speaker: Dr. John Jose, Associate Professor, Indian Institute of Technology Guwahati,

Date/Time: Aug 04 15:00:00

Location: CSA Class (Room No. 252, First Floor)

Abstract:
Tiled Chip Multi-Processors (TCMP) is one of variant of Multiprocessor System on Chips (MPSoCs) MPSoC that uses Network on Chip (NoC) for inter tile communication. NoC is a multi-hop packet-based communication infrastructure that connects different cores with each other through routers. NoC provides a high transfer bandwidth, and the infrastructure is scalable. Applications running on different cores access on-chip last level cache memories and off-chip main memory through the underlying NoC. As NoC plays a vital role in memory access latency, ignoring the nature of its infrastructure may severely impact the performance of the applications in TCMPs. This talk attempts to share some thoughts on a few architectural optimizations done to establish a dynamic cooperation between NoC and the memory hierarchy for improved performance. By gathering information about the data travelling from one level of memory to another, we exploit underutilized NoC resources to design techniques and propose optimizations that reduce memory access latency and improve overall system performance.

Speaker Bio:
Dr. John Jose is an Associate Professor in Department of Computer Science & Engineering, Indian Institute of Technology Guwahati, where he joined as an Assistant Professor in 2015. He completed his Ph.D degree from Indian Institute of Technology Madras in the field of computer architecture. He was a rank holder in M.Tech degree from Vellore Institute of Technology (VIT University). He did his B.Tech degree from College of Engineering Adoor, Cochin University, Kerala. He is the recipient of the prestigious Qualcomm Faculty Award 2021. He is also serving as the Vice-Chair of IEEE India Council. His research group in Multicore Architecture and Systems Lab at IITG explores the domain of network on chips, cache management techniques for large multicore systems, non-volatile memories, hardware security, domain specific hardware accelerators and disaggregated storage systems. He is the associated editor for IEEE-Embedded System Letter Journal. He has over 50 IEEE & ACM peer reviewed conference publications, over 15 ACM & IEEE transactions papers as well as Springer and Elsevier journal papers to his credit. He is a reviewer for many national and international peer reviewed journals and member of technical program committee and organizing committee for many IEEE/ACM national and international conferences. He is the investigator for several R&D projects under DST and MeitY. He is associated with many national pilot projects like NPTEL-MOOCS, SPARC, GIAN, TEQIP, ISEA, Ishan Vikas, Vigyan Jyoti etc. He has active academic research collaboration with University of Catania, Italy, University of Florida, USA, University of Essex, UK, Federal University Naples, Italy and Qualcomm India. He has offered two popular NPTEL Online Certification courses in the area of Computer Architecture. He was the recipient of ACM-SIGDA, IEEE-CEDA, IARCS and DRDO research grants for technical presentations in various international forums. He is a resource person for computer architecture and hardware security related symposia, workshops, short-term courses and faculty development programs in many organizations across the country. He is an invited speaker for many career guidance seminars/ teaching pedagogy workshops to various technical institutes, R&D houses and schools. He is also serving as Board of Studies members to various universities and autonomous colleges. He is an active member of professional societies like ACM, IEEE, ISTE and CSI.

Host Faculty: Dr. Sumit Kumar Mandal