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Wafer-Scale processing for AI and HPC

Series: Department Seminar

Speaker: Harinath Kamepalli Senior Director of Software Cerebras Systems

Date/Time: Jun 03 15:00:00

Location: CSA Seminar Hall (Room No. 254, First Floor)

Abstract:
As ML algorithms and network architectures evolve rapidly to improve performance for variety of applications, some trends are very clear: larger models are often highly effective, compute and memory requirements are growing exponentially, scale-out based approaches are yielding sub-linear results, deep expertise is needed to achieve high utilization on scale-out. These trends motivate for Wafer-Scale chip with distributed memory architecture and a domain specific ISA for ML applications. It turns out that this architecture can also offer compelling performance advantage on some HPC applications. This talk covers some of the key details of Cerebras Wafer-Scale Engine (WSE) based accelerator and how it accelerates AI and HPC applications.

Speaker Bio:
Harinath Kamepalli is Senior Director of Software at Cerebras Systems. Since joining the team in Jan 2018, he has been working on building the end-to-end SW platform for multiple generations of Wafer Scale Engine (WSE) based CSx systems. His primary focus is leading SW teams working on core compiler technologies, optimized kernel libraries, and performance modeling and optimization. Prior to joining Cerebras Systems, he worked on building compilers for accelerating compute intensive Electronic Design Automation (EDA) applications such as simulation and emulation on CPUs, FPGAs, and GPUs.
Microsoft team link:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_YWEzNjBiNTAtMjk1Yi00YWJlLTk2MTgtOWM0OWM2NGQ4YjFj%40thread.v2/0?context=%7b%22Tid%22%3a%226f15cd97-f6a7-41e3-b2c5-ad4193976476%22%2c%22Oid%22%3a%22c747ccaa-ceaa-4197-b4cb-ce2f1d4694da%22%7d

Host Faculty: Prof. Uday Kumar Reddy .B