Seminars

View all Seminars  |  Download ICal for this event

An MLIR-based High-level Synthesis Compiler for Hardware Accelerator Design

Series: Ph.D. Thesis Defense

Speaker: Kingshuk Majumder, Ph.D (Engg.) student Dept. of C.S.A

Date/Time: Jul 27 11:00:00

Location: CSA Class (Room No. 252, First Floor)

Faculty Advisor: Prof. Uday Kumar Reddy B

Abstract:
The emergence of machine learning, image and audio processing on edge devices
has motivated research towards power-efficient custom hardware accelerators.
Though FPGAs are an ideal target for custom accelerators, the difficulty of
hardware design and the lack of vendor-agnostic, standardized hardware
compilation infrastructure has hindered their adoption.
High-level synthesis (HLS) offers a more compiler-centric alternative to the
traditional Verilog-based hardware design improving developer productivity.

In this work, we propose an MLIR-based end-to-end HLS compiler and an
an intermediate representation that is suitable for the design and implementation of
domain-specific accelerators for affine workloads. Our compiler brings similar
levels of modularity and extensibility to the HLS compilation domain, which
LLVM brought to the area of a software compilation.
A modular compiler infrastructure offers the advantage of incrementally
introducing new language frontends and optimization passes without the need to
reinvent the whole HLS compiler stack.

Our compiler converts a high-level description of the accelerator specified in
the C programming language into a register-transfer-level design
in SystemVerilog. We use memory dependence analysis and
integer-linear-program(ILP) based automatic scheduling on improving loop-pipelining and
introduce parallelization between producer-consumer kernels.
Our ILP-based optimizer beats the state-of-the-art Vitis HLS compiler by 1.3x
in performance over a representative set of benchmarks while requiring fewer
FPGA resources.

Microsoft teams link:

Link